Teradyne, Inc. seeks Semiconductor Design Engineer in Tualatin, OR
- Design and implement register-transfer-level (RTL) code for FPGAs
- Oversee simulation, verification, and test bench development for RTL designs
- Develop requirements and interface specification for FPGA designs
- Conduct synthesis, place-and-route, and timing closure for FPGA designs
- Conduct lab validation of FPGA designs
Telecommuting Permitted.
$121,680 - $156,700 per year.
To apply: Visit https://www.jobpostingtoday.com/application/99834/apply
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